TPS3813K33DBVT

The TPS3813K33DBVT is a Supervisory Circuit with active-low open-drain output. The supervisory circuit provides circuit initialization and timing supervision, primarily for DSPs and processor-based systems. During power on, /RESET is asserted when supply voltage (VDD) becomes higher than 1.1V. Thereafter, the supervisory circuit monitors VDD and keeps /RESET active as long as VDD remains below the threshold voltage (VIT). An internal timer delays the return of the output to the inactive state (high) to ensure proper system reset. The delay time (td) of 25ms typical, starts after VDD has risen above the threshold voltage (VIT). When the supply voltage drops below the threshold voltage (VIT), the output becomes active (low) again. No external components are required. It has a fixed-sense threshold voltage (VIT) set by an internal voltage divider.